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Da ta S heet, V1.3, Dec. 2000
C505CA-4RC Step BB
8-bit Single-Chip Microcontroller (Bare Die Delivery)
M i c r o c o n t ro l le r s
Never
stop
thinking.
Edition 2000-12 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2000.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Da ta S heet, V1.3, Dec. 2000
C505CA-4RC Step BB
8 - b i t S i n g l e -C h i p M i c r o c o n t ro l le r (Bare Die delivery)
M i c r o c o n t ro l le r s
Never
stop
thinking.
C505CA-4RC (Bare Die Delivery) Revision History: Previous Version: Page 14 2000-12 V1.2, V1.1 V1.3
Subjects (major changes since last revision) Reference of Data Sheet version is updated
Controller Area Network (CAN): License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
8-bit Single-Chip Microcontroller C500 Family Advance Information
* Fully compatible to standard 8051 microcontroller * Superset of the 8051 architecture with 8 datapointers * Up to 20 MHz operating frequency - 375 ns instruction cycle time @16 MHz - 300 ns instruction cycle time @20 MHz (50% duty cycle) * On-chip program memory (with optional memory protection) - 32K byte on-chip Mask ROM - alternatively up to 64k byte external program memory * 256 byte on-chip RAM * 1K byte On-chip XRAM (more features on next page)
C505CA-4RC
On-Chip Emulation Support Module
Oscillator Watchdog A/D Converter
(10-bit)
XRAM 1K byte Timer 0 Timer 1
RAM
256 byte
Port 0 Port 1
I/O 8 analog inputs / 8 digit. I/O I/O I/O I/O (2-bit I/O port)
Timer 2 Full-CAN Controller Watchdog Timer
C500 Core
8 Datapointers
8-bit USART Port 2 Port 3
Program Memory C505CA-4RC: 32K byte ROM C505CA-LC: ROMless
Port 4
Figure 1
C505CA-4RC Functional Units
Data Sheet
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Features(continued) : * 32 + 2 digital I/O lines - Four 8-bit digital I/O ports - One 2-bit digital I/O port (port 4) - Port 1 with mixed analog/digital I/O capability * Three 16-bit timers/counters - Timer 0 / 1 (C501 compatible) - Timer 2 with 4 channels for 16-bit capture/compare operation * Full duplex serial interface with programmable baudrate generator (USART) * Full CAN Module, version 2.0 B compliant - 256 register/data bytes located in external data memory area - 1 MBaud CAN baudrate when operating frequency is equal to or above 8 MHz - internal CAN clock prescaler when input frequency is over 10 MHz * On-chip A/D Converter - up to 8 analog inputs - 10-bit resolution * Twelve interrupt sources with four priority levels * On-chip emulation support logic (Enhanced Hooks Technology TM1)) * Programmable 15-bit watchdog timer * Oscillator watchdog * Fast power on reset * Power Saving Modes - Slow-down mode - Idle mode (can be combined with slow-down mode) - Software power-down mode with wake up capability through P3.2/INT0 or P4.1/ RXDC pin * Temperature ranges: SAB-C505 versions TD = 0 to 70 C SAF-C505 versions TD = -40 to 85 C SAK-C505 versions TD = -40 to 125 C SAA-C505 versions TD = -40 to 150 C
1)
"Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Infineon Technologies.
Data Sheet
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Ordering Information
Table 1 Type
Bare Die Ordering Information Ordering Code TBD Wafers Whole/Sawn Comments 8-bit microcontroller with Temperature range: -40 C to +125 C (max. operating frequency: 20 MHz with 50% duty cycle) 8-bit microcontroller with Temperature range: -40 C to +150 C (max. operating frequency: 20 MHz with 50% duty cycle) 8-bit microcontroller with 32K bytes ROM Temperature range: -40 C to +125 C (max. operating frequency: 20 MHz with 50% duty cycle) 8-bit microcontroller with 32K bytes ROM Temperature range: -40 C to +150 C (max. operating frequency: 20 MHz with 50% duty cycle)
SAK-C505CA-LC
SAA-C505CA-LC
TBD
Whole/Sawn
SAK-C505CA-4RC
TBD
Whole/Sawn
SAA-C505CA-4RC
TBD
Whole/Sawn
Note: The ordering codes for the Mask-ROM versions (DXXXX extension) are defined for each product after verification of the respective ROM code. Note: Versions for the temperature range 0 C to 70 C (SAB-C505) and -40 C to 85 C (SAF-C505) are available on request.
Data Sheet
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Introduction The C505CA-xC derivatives, which refer to C505CA-4RC and C505CA-LC in this document, are high performance derivatives of the Infineon C500 family of 8-bit microcontrollers. The C505CA-xC derivatives are fully compatible to the standard 8051 microcontroller. Additionally the C505CA-xC provides extended power save provisions, on-chip RAM, 1K byte XRAM, on-chip ROM, 10-bit A/D converter, and RFI related improvements.
VDD
VSS
VAREF VAGND XTAL1 XTAL2 RESET EA ALE PSEN
Port 0 8-bit Digital I/O Port 1 8-bit Digital I/O / 8-bit Analog Inputs Port 2 8-bit Digital I/O Port 3 8-bit Digital I/O Port 4 2-bit Digital I/O
C505CA-4RC C505CA-LC
Figure 2
Logic Symbol
Data Sheet
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Pad Configuration
Pad 38 Pad 39
Pad 28 Pad 27 C505CA-4RC
y
0.0 Pad 1 x 0.0
Figure 3 C505CA-4RC Pad Configuration (Top View)
Pad 49
Pad 11
Data Sheet
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Pad 12
C505CA-4RC Step BB
Table 2
Pad Definition and Functions Function
Symbol Pad In/ Position Num. Out [m] (I/O) x y P1.5 1 I/O 453 0
Port 1 general Input/Output (quasi-bidirectional)/ Analog input channel 5 / Timer 2 external reload / trigger input Port 1 general Input/Output (quasi-bidirectional)/ Analog input channel 6 / system clock output Port 1 general Input/Output (quasi-bidirectional)/ Analog input channel 7 / counter 2 input RESET input Port 3 general Input/Output (quasi-bidirectional)/ Receiver data input (asynch.) or data input/ output (synch.) of serial interface Port 4 general Input/Output (quasi-bidirectional)/ Transmitter output of CAN controller Port 3 general Input/Output (quasi-bidirectional)/ Transmitter data output (asynch.) or clock output (synch.) of serial interface Port 3 general Input/Output (quasi-bidirectional)/ External interrupt 0 input / timer 0 gate control input Port 3 general Input/Output (quasi-bidirectional)/ External interrupt 1 input / timer 1 gate control input Port 3 general Input/Output (quasi-bidirectional)/ Timer 0 counter input Port 3 general Input/Output (quasi-bidirectional)/ Timer 1 counter input Port 3 general Input/Output (quasi-bidirectional)/ WR control output Port 3 general Input/Output (quasi-bidirectional)/ RD control output Output of the inverting oscillator amplifier.
P1.6 P1.7 RESET P3.0
2 3 4 5
I/O I/O I I/O
753 1053 1284 1451
0 0 0 0
P4.0 P3.1
6 7
I/O I/O
1796 2012
0 0
P3.2
8
I/O
2201
0
P3.3
9
I/O
2586
0
P3.4 P3.5 P3.6 P3.7 XTAL2
10 11 12 13 14
I/O I/O I/O I/O O
2886 3547 3991 3991 3991
0 0 484 778 1028
Data Sheet
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Table 2
Pad Definition and Functions Function
Symbol Pad In/ Position Num. Out [m] (I/O) x y XTAL1 NC VSS VSS VSS VDD VDD VDD P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN ALE P4.1 EA 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 I I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I 3991 3991 3991 3991 3991 3991 3991 3991 3991 3991 3991 3991 3991 3537 3165 2785 2505 2186 1886 1588 1193 1355 1480 1605 1730 1904 2029 2155 2289 2423 2664 2980 3295 3739 3739 3739 3739 3739 3739 3739
Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Not connected Ground (0V) Ground (0V) Ground (0V) Power Supply (+5V) Power Supply (+5V) Power Supply (+5V) Port 2 general Input/Output (quasi-bidirectional)/ High-order address byte line A8 Port 2 general Input/Output (quasi-bidirectional)/ High-order address byte line A9 Port 2 general Input/Output (quasi-bidirectional)/ High-order address byte line A10 Port 2 general Input/Output (quasi-bidirectional)/ High-order address byte line A11 Port 2 Input/Output (quasi-bidirectional)/ High-order address byte line A12 Port 2 general Input/Output (quasi-bidirectional)/ High-order address byte line A13 Port 2 general nput/Output (quasi-bidirectional)/ High-order address byte line A14 Port 2 general Input/Output (quasi-bidirectional)/ High-order address byte line A15 Program Store Enable Address Latch Enable Port 4 general Input/Output (quasi-bidirectional)/ Receiver input of CAN controller External Access Enable
Data Sheet
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Table 2
Pad Definition and Functions Function
Symbol Pad In/ Position Num. Out [m] (I/O) x y P0.7 35 I/O 1327 3739
Port 0 general Input/Output (open-drain)/ Multiplexed low-order address and data bus line A7/D7 Port 0 general Input/Output (open-drain)/ Multiplexed low-order address and data bus line A6/D6 Port 0 general Input/Output (open-drain)/ Multiplexed low-order address and data bus line A5/D5 Port 0 general Input/Output (open-drain)/ Multiplexed low-order address and data bus line A4/D4 Port 0 general Input/Output (open-drain)/ Multiplexed low-order address and data bus line A3/D3 Port 0 general Input/Output (open-drain)/ Multiplexed low-order address and data bus line A2/D2 Port 0 general Input/Output (open-drain)/ Multiplexed low-order address and data bus line A1/D1 Port 0 general Input/Output (open-drain)/ Multiplexed low-order address and data bus line A0/D0 Reference voltage for the A/D converter. Reference ground for the A/D converter. Port 1 general Input/Output (quasi-bidirectional)/ Analog input channel 0 / interrupt 3 input / capture/compare channel 0 I/O Port 1 general Input/Output (quasi-bidirectional)/ Analog input channel 1 / interrupt 4 input / capture/compare channel 1 I/O
P0.6
36
I/O
1078
3739
P0.5
37
I/O
744
3739
P0.4
38
I/O
444
3739
P0.3
39
I/O
0
3295
P0.2
40
I/O
0
2936
P0.1
41
I/O
0
2586
P0.0
42
I/O
0
2322
VAREF VAGND P1.0
43 44 45
I/O
0 0 0
2078 1878 1652
P1.1
46
I/O
0
1370
Data Sheet
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Table 2
Pad Definition and Functions Function
Position Symbol Pad In/ Num. Out [m] (I/O) x y P1.2 47 I/O 0 1129
Port 1 general Input/Output (quasi-bidirectional)/ Analog input channel 2 / interrupt 5 input / capture/compare channel 2 I/O Port 1 general Input/Output (quasi-bidirectional)/ Analog input channel 3 /interrupt 6 input / capture/compare channel 3 I/O Port 1 general Input/Output (quasi-bidirectional)/ Analog input channel 4
P1.3
48
I/O
0
776
P1.4
49
I/O
0
453
Note: All VSS pads and all VDD pads must be connected to the system ground and the power supply, respectively. The pad definitions and locations in this table are only valid for the indicated device and design step. Handling Of Unconnected Pads Signal input stages may generate undesired switching noise and cross-current when left open. Respect the following precautions for unconnected (not bonded) pads: Table 3 Pad Type Power Supply Standard I/O pads(except P0) Port 0 Required control lines Optional control lines Precautions for Unconnected Pads Recommended Action Always connect! Can be left Set the corresponding pad latches to '0's Always connect! Can be left open Related Pads VDD, VSS, VAREF, VAGND P11), P2, P3, P4 P0 RESET, XTAL1,EA ALE, PSEN, XTAL2
1) Avoid to set unconnected P1 pad as analog input if left open. However, P1 is set as digital I/O by default after reset.
Data Sheet
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Functional Description As the standard packaged devices are made from this silicon the C505CA-xC dies provide exactly the same functionality and behaviour. Also the DC characteristics and AC characteristics are compatible with those of the packaged devices. For a description of the functionality and the DC and AC parameters please refer to the following documents (or later versions thereof): * C505/C505C/C505A/C505CA Data Sheet 2000-12 * C505/C505C User's Manual 08.97 * C505A/C505CA User's Manual 09.97 (Addendum to C505/C505C)
Data Sheet
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VDD Vss XTAL1 XTAL2 Oscillator Watchdog XRAM
1K Byte
RAM
256 Byte
ROM
32k Byte
OSC & Timing
RESET ALE PSEN EA
CPU 8 datapointers
Programmable Watchdog Timer
Timer 0
Port 0
Port 0 8-bit digit. I/O Port 1 8-bit digit. I/O / 8-bit analog In Port 2 8-bit digit. I/O
Port 1 Timer 1 Port 2
Timer 2 USART
Baudrate generator
Port 3
Port 3 8-bit digit. I/O Port 4 2-bit digit. I/O
Full-CAN Controller
256 Byte Reg./Data
Port 4
Interrupt Unit VAREF VAGND
A/D Converter (10-Bit) S&H MUX
Emulation Support Logic
Figure 4
Block Diagram
Data Sheet
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Absolute Maximum Ratings
Parameter Storage temperature Voltage on VDD pins with respect to ground (VSS) Voltage on any pin with respect to ground (VSS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Power dissipation
Symbol min. TST VDD VIN - 65 - 0.5 - 0.5 - 10
Limit Values max. 150 6.5
VDD + 0.5
Unit Notes C V V mA mA - - - - -
10 | 100 mA |
PDISS
1
W
-
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Data Sheet
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Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operatinon of the C505CA-xC. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Operating Conditions Parameter Supply voltage Ground voltage Temperature of the bottom side of the die SAB-C505 TD SAF-C505 TD SAK-C505 TD SAA-C505 TD Analog reference voltage Analog ground voltage Analog input voltage XTAL clock
VAREF VAGND VAIN
Symbol Limit Values min. VDD VSS 4.25 2 0 max. 5.5 5.5
Unit Notes V V V Active mode PowerDown mode Reference voltage -
C
0 -40 -40 -40 4
VSS - 0.1 VAGND -0.2
70 85 125 150
VDD + 0.1 VSS + 0.2 VAREF +0.2
V V V
- - -
fosc
2
20 (with 50% duty cycle)
MHz -
Data Sheet
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Storage Conditions The C505CA-xC dies may be stored for a certain time under the conditions described below. Table 4 Packing Vacuum pack Bare Die Storage Conditions and Duration Environment Air Temperature 15...30 C Rel. Humidity < 60 % Storage Time < 4 Months
Power Supply Currents The power supply currents for the bare die are compatible with those of the packaged devices with the following exceptions: * The maximum Power down current (IPD) for bare die is: IPD MAX. = 35 uA
Data Sheet
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Bare Die Outline
0.38
3.873 (excluding scribeline) 4.125 (excluding scribeline) 4.235 (including scribeline) y x 0,0 0.090 0.125 min 0.090 Figure 5
Data Sheet
Typical Dimensions in mm
Bare Die Outline
19 V1.3, 2000-12
3.983 (including scribeline)
C505CA-4RC Step BB
Table 5 Item
Wafer Characteristics Characteristic 820 2 AICu Met1: 450 nm, Met2: 800 nm Ti/Tin FLOW-FILL AICu (AI 99.5% - Cu 0.5%) Si-Oxide (310 nm) + Si-Nitride (510 nm) None (silicon) 1.0-1.3 mm (typical)
Chips per wafer Metallization layers Metallization material Metallization thickness Metallization barrier material Metallization isolation Metallization material on pads Passivation Backside metallization Inkdot diameter
The wafers are glued to a plastic tape which is fixed within a plastic ring (see figure below). Wafers can be shipped in one piece or sawn into individual dies.
Data Sheet
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Wafer Outline
Plastic Frame Plastic Tape Wafer
152.4 (6") 210 230 Dimensions in mm Figure 6 Wafer Outline
Data Sheet
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